Laminates are used as carriers for silicon chips (integrated circuits) which are used in dual in-line packages for integrated circuits. The dual in-line packages in typical fashion are components small in size, measuring in some instances 1".times.1/2" and have integrated circuitry silicon chips mounted on these packages. The silicon chips are programmable so that they carry or maintain a bank of information and must be electrically connected to the circuit board so that the information contained in the chip can be passed through the circuit board to control various electrical and electronic devices such as computers, instruments, communication devices, airplane guidance systems, etc.
In view of the complexity of the circuitry, it is advantageous to reduce the area which is required to hold a given amount of information. One method of accomplishing this goal is to change the method of packaging and attaching the integrated circuitry chips to the circuit board. The relatively large dual in-line packages, that is, packages which are as large as 1".times.3", ordinarily have leads that plug into plates through holes in the circuit board and should, in order to render the circuit more efficient, be replaced by more compact integrated circuitry chips. For example, some dual in-line packages have as many as 64 leads and instead of inserting all of these leads into the circuit board, the latest construction circuitry is to package some of the integrated circuitry chips into chip carriers which are then mounted to the circuit board surface. This eliminates the cumbersome process of plugging all the leads into holes in the circuit board and provides an easier process for connecting the chip to the circuit board. In addition to providing this easier process, it is possible to increase the number of leads and concurrently increase the amount of information that can be transmitted from a given area on the circuit board.
Heretofore, silicon chips have been mounted on a chip carrier such as ceramics or plastics which, in turn, have been mounted on a chip carrier substrate or circuit board. However, in some instances, it is important that the chip carrier is hermetically sealable. Only ceramic chip carriers are hermetically sealable in today's state of the art. The coefficient of thermal expansion of ceramic is 6.4.times.10.sup.-6 in/in/.degree.C. The CTE of standard laminates is 13-15.times.10.sup.-6 in/in/.degree.C. This thermal mismatch results in the inability of the package to be able to withstand temperature cycling. The reason for this is that when the package (the silicon chip which is mounted to the chip carrier which is, in turn, mounted to the chip carrier substrate) is subjected to temperature extremes, the solder joints may fracture due to the varying thermal expansion properties of the current materials involved with the resulting disadvantage that an electrical open occurs. The electrical open occurs when stress is produced due to the temperature fluctuations, the stress being exerted on the solder joints which connect the materials inasmuch as said materials expand and contract at different rates. After repeated temperature cycling, the solder joint can break, thus causing the electrical open. In order to minimize the aforementioned stress which is exerted on the solder joint, it is necessary to utilize a chip carrier and a chip carrier substrate which will have the same rate or minimally different rates of expansion and contraction. This will insure that the solder joints will not fracture during the thermal cycling.
Another area in which thermal expansion plays an important role is that of multi-layer laminated boards which may be used as printed wiring boards which are utilized as components in various electrical and electronic devices. A major problem which is attendant with many of these laminates which are made of multilayer substrates is the dimensional stability of the inner layers of the composite board. For example, a multilayer board may consist of up to 20 layers of substrate materials. When processing these inner layers to form the desired board substrate, the layers are subjected to a thermal stress. During this thermal stress, the inner layers may expand or contract. For example, when utilizing a glass cloth such as a fiberglass cloth, the cloth will exert an effect on the dimensional stability of the inner layers. In this respect, a glass cloth which will expand more than 0.0005 inch/inch will cause registration problems of the pads in the various layers, said poor registration resulting in the inability to connect the inner layers which is cause for either failure or rejection.
It is therefore readily apparent that if a material can be obtained which possesses a better dimensional stability, the material may be used in preparing carrier substrates for silicon chips as well as being used as a component in preparing multilayer printed wiring boards. It has now been discovered that a hybrid glass cloth which is woven from certain materials will possess the desired thermal dimensional stability and thus may be used as chip carrier substrates and dimensionally stable laminates.